An inverter circuit for driving a load such as a motor is a switching equipment between direct current and alternating current, converts the direct current to the alternating current and feeds the alternating current voltage into the motor as the load. The inverter circuit for driving an inductive motor includes a MOS transistor as a switching element and a free wheel diode. The MOS transistor is used as the switching element and the free wheel diode functions that current flowing in the motor does not change due to the switching of the MOS transistor by bypassing the current flowing in the motor at the off-state of the MOS transistor. Hereinafter, although the switching element will be described by using the MOS transistor, but the switching element may be an insulated gate bipolar transistor (IGBT).
FIG. 15 is a cross sectional view of a semiconductor device 90. The semiconductor device 90 is used for the above-mentioned inverter circuit for driving a load such as a motor, and is an example of a semiconductor device including a MOS transistor cell and a diode cell, which are provided over the same substrate. It is shown by the inventors as a comparative example of the present disclosure. In addition, FIG. 16 is an equivalent circuit diagram of the semiconductor device 90 shown in FIG. 15.
In the semiconductor device 90 shown in FIG. 15, a p-conductive type (P) layer 2 is formed over a surface portion on a main side of an n-conductive type (N−) semiconductor substrate 1, and a main side n-conductive type (N+) region 3 having an impurity at high concentration and a main side high concentration p-conductive type (P+) region 4 are formed in a surface portion of the p-conductive type layer 2. Moreover, a rear side n-conductive type (N+) region 6 is formed over a surface portion on a rear side of the n-conductive type semiconductor substrate 1.
In the semiconductor device 90 shown in FIG. 15, a first trench T1 which reaches the n-conductive type semiconductor substrate 1 is formed to penetrate the main side n-conductive type region 3 and the p-conductive type layer 2.
In the semiconductor device 90 shown in FIG. 15, a first electrode layer 8 made of polysilicon or the like, which is embedded in the first trench T1 through an insulating film 7 formed over a sidewall, provides a gate electrode of a MOS transistor cell 90t. A second electrode layer 10 made of aluminum or the like is formed over the main side of the n-conductive type semiconductor substrate 1 through an interlayer insulating film 9. The second electrode layer 10 is electrically coupled with the p-conductive type layer 2 through the main side n-conductive type region 3 and the main side p-conductive type region 4, and provides a source electrode of the MOS transistor cell 90t and an anode electrode of a diode cell 90d. Moreover, a third electrode layer 11, which is formed over the rear side surface of the n-conductive type semiconductor substrate 1 and being electrically coupled with the rear side n-conductive type region 6, provides a drain electrode of the MOS transistor 90t and a cathode electrode of the diode cell 90d. 
In other words, in the semiconductor device 90, the main side n-conductive type region 3 is a source region of the MOS transistor cell 90t, the p-conductive type layer 2 is a channel forming layer of the MOS transistor cell 90t, and the rear side n-conductive type region 6 is a drain region of the MOS transistor cell 90t. Moreover, an interface between the n-conductive type semiconductor substrate 1 and the p-conductive type layer 2 is a PN junction surface of the diode cell 90d, the main side p-conductive type region 4 is an anode region of the diode cell 90d, and the rear side n-conductive type region 6 is a cathode region of the diode cell 90d. Therefore, as shown by the equivalent circuit diagram in FIG. 16, in the semiconductor device 90, the MOS transistor cell 90t and the diode cell 90d are connected in parallel to each other.
In case that the diode cell 90d of the semiconductor device 90 in FIG. 15 is used as the above-mentioned free wheel diode of the inverter circuit, the current waveform at reverse recovery step of the diode is important when the diode is switched from on-state to off-state.
FIG. 18A is a circuit diagram for measuring and evaluating a current waveform of the current flowing in the diode cell 90d of the semiconductor device 90 shown in FIG. 15, and FIG. 18B is a diagram showing an example of a current waveform.
Semiconductor devices 90a and 90b in the measuring circuit diagram of FIG. 18A have the same structure as the semiconductor device 90 shown in FIG. 15. A MOS transistor 90 at of the semiconductor device 90a is used as a switching element, and the waveform of the current Id flowing in a diode 90bd is measured by short-circuiting the MOS transistor of the semiconductor device 90b. 
As shown in FIG. 18B, when the MOS transistor 90 at of the semiconductor device 90a is in an off-state, circulation current Iif flows in the diode 90bd of the semiconductor device 90b. The MOS transistor 90 at of the semiconductor device 90a is switched to be in an on-state, current flows instantaneously in a reverse direction in the diode 90bd of the semiconductor device 90b. The peak value of the current flowing in the reverse direction is defined as the recovery current Irr. In addition, at the reverse recovery step, in which the recovery current is small, the diode is applied supply voltage. The product of the current and the voltage is defined as the recovery loss. Generally, it is required for a rectifier diode to have a small recovery current Irr, small recovery loss at the reverse recovery step, and gradual recovery of the current at the reverse recovery step.
In the semiconductor device 90 shown in FIG. 15, the diode cell 90d provided with the MOS transistor 90t, in which the interface between the p-conductive type layer 2 of the MOS transistor cell 90t and the n-conductive type semiconductor substrate 1 provides the PN junction surface, operates as a free wheel diode. In the diode cell 90d of the semiconductor device 90, the concentration of the p-conductive type layer 2 which configures the diode becomes high as compared with a common high-speed recovery diode. Thus, holes are injected at high concentration when the diode cell 90d is at the forward operation and the recovery current Irr becomes large at the recovery operation. Therefore, the recovery property becomes worse.
In order to improve the recovery property of the diode, a method that a surface pattern, a concentration profile of an impurity and lifetime or the like are optimized can be applied to a single high-speed diode. However, in the diode cell 90d of the semiconductor device 90, which is provided with the MOS transistor cell 90t, modification for improving the performance of the diode cell 90d may impair the performance of the MOS transistor cell 90t. Therefore, the above-mentioned method can not be applied.
A structure of a semiconductor device for improving the recovery property is disclosed in JP-A-2005-101514.
FIG. 17 is a view showing a commonly known structure including the structure of a semiconductor device disclosed in JP-A-2005-101514 and a cross sectional view of a semiconductor device 91. In the semiconductor device 91 of FIG. 17, with respect to the same component with one included in the semiconductor device 90 of FIG. 15, the same reference numerals are applied.
In the semiconductor device 91 shown in FIG. 17, a channel forming region of a MOS transistor cell 91t is formed by a p-conductive type region 2w which is laterally diffused, and a PN junction surface of a diode cell 91d is used as an interface of an n-conductive type (N−) semiconductor substrate 1 in vicinity of an end portion of the p-conductive type region 2w which is laterally diffused in a lateral direction. Since the impurity concentration in the vicinity of the end portion of the p-conductive type region 2w, which is laterally diffused in the lateral direction, is low, a concentration of injected holes is decreased when the diode cell 91d is at the forward operation, so that the recovery property is improved.
Unlike the semiconductor device 90 shown in FIG. 15, the main side p-conductive type (P+) region 4 is not formed in the semiconductor device 91 shown in FIG. 17. Moreover, an impurity concentration of a surface of the p-conductive type region 2w, which is laterally diffused of the semiconductor device 91 in FIG. 17, is low compared to the p-conductive type layer 2 of the semiconductor device 90 shown in FIG. 15. Therefore, in the semiconductor device 91 of FIG. 17, a pinch resistance of a channel P (the p-conductive type region 2w), which is a base resistance of a parasitic NPN transistor structured by the main side n-conductive type (N+) region 3, the p-conductive type region 2w and the n-conductive type semiconductor substrate 1, becomes large. As a result, since a current amplification factor of the parasitic NPN transistor becomes large, when a high voltage surge is applied to the semiconductor device 91 and an avalanche current flows in the p-conductive type region 2w, the parasitic NPN transistor is easy to operate and the semiconductor device 91 is broken by the high voltage surge. That is, although the recovery property of the diode cell 91d of the semiconductor device 91 in FIG. 17 is improved, a breaking energy becomes very small and a surge withstand property becomes low.